The present invention relates to circuits for storing representations of data and, more particularly, to such circuits used in monolithic integrated circuits which are subject to transient event disturbances.
There are many uses in digital systems for data storage circuits, i.e. data latches. Such latches are used frequently to store a signal value representing data received at a data input for a duration of time after an enabling signal of a particular logic value has also been received at an enable input. This arrangement is useful, for instance, in permitting subsequent portions of the digital system to operate on a fixed value signal at the output of the latch even though further changes are occurring at the latch data input.
Such data latches are commonly provided in monolithic integrated circuits, along with many further kinds of other circuitry, for purposes of improving performance, reducing size and reducing cost. Monolithic integrated circuit structural features arising in the implementation of such circuits have been shrinking rapidly in size in recent years. Along with this shrinkage, the electrical currents and electrical charges formed during the operation of the integrated circuits based on these features have also been diminishing in value. As a result, charges generated by certain charge generating disturbances, which in larger feature integrated circuits would not be a problem, become sufficiently large to cause difficulties in smaller feature integrated circuits.
In those voltage level state switching circuits, such as logic circuits or memory circuits including such data latch circuits, that are constructed using these smaller integrated circuit structures, such disturbance charges can be sufficient to cause switching from an existing logic state to another at points on the circuit where such charge is generated. The proper operation of the circuit could therefore be disturbed resulting in erroneous logic signals. Typically, such disturbances are local to the region near the disturbance and are temporary; thus, such a disturbance is often termed a "single event upset." Also, though the disturbances may be temporary, results of the disturbance may be stored and are subject to being propagated further in the system which may lead to longer term and more significant effects.
A common source of such charge generating disturbances is particle radiation. Such particles impinging on a monolithic integrated circuit chip will have "interactions" with the semiconductor material lattice structure and electrons along the paths thereof through the integrated circuit semiconductor material. This will result, for the short duration of these interactions, in raising the energy of the electrons involved in the conduction band and leaving corresponding holes in the valence band. Should such electron-hole pairs be generated sufficiently close to a semiconductor pn junction, the electrons and holes so situated are subject to being collected by the action of electric fields in the region resulting from the voltage applied to such junction and because of diffusions toward such junctions. The structure of transistor devices used in a monolithic integrated circuit, and the methods of operating such devices in the circuits using them generally, is such that only reverse-biased pn junctions need to be considered to understand the effects of a radiation particle impinging thereabout.
The electrons and corresponding holes will be separated by the electric fields near the reverse-biased junction with the electrons attracted to the positive voltage side of the junction and the holes being attracted, or repelled, into the portions of the semiconductor material on the other side of the junction. This separation of electrons and holes, in effect, provides a temporary current flow from the positive voltage side of the semiconductor pn junction to the opposite side of the structure, or, in effect, a radiation induced leakage current.
This current will be comprised of an immediate drift current component for electrons and holes which are immediately subject to such electric fields. A further component of this current will be provided by those electrons and holes which subsequently, by diffusion, move to be within the influence of such electric fields. Such current flows have the effect of discharging an n-type conductivity region if that region has been placed at a positive voltage with respect to a p-type conductivity region on the other side of the intervening junction so that this junction is reverse-biased. Such a discharge current reduces the positive voltage of the n-type region. Conversely, such currents tend to charge a p-type conductivity region, if that region has been placed at a negative voltage with respect to an n-type conductivity region on the other side of an intervening semiconductor pn junction to again reverse-bias that junction. Such a charging acts to reduce the negative voltage to thereby reduce the reverse-bias across the junction. Thus, in either situation, the charge generated by an impinging radiation particle would act in a manner to tend to reduce the magnitude of reverse-bias voltages provided across a reverse-biased semiconductor pn junction separating p-type conductivity and n-type conductivity regions suffering such an impingement.
One known data latch is the controlled latch circuit shown in FIG. 1. In that circuit, a pair of input npn bipolar transistors, 10 and 11, are provided with transistor 10 having its base connected to an input terminal, 12, and transistor 11 having its base connected to a further input terminal, 13. Input transistor 10 is paired with a further npn bipolar transistor, 14. Input transistor 11 is also paired with another npn bipolar transistor, 15. The collectors of transistors 10 and 14 are connected to one another and to a load resistor, 16. Similarly, the collectors of transistors 11 and 15 are connected together and to another load resistor, 17. The collectors of transistors 10 and 14 are also connected to the base of an output npn bipolar transistor, 18, for that pair, and again the collectors of transistors 11 and 15 are also connected to an output transistor, 19, for that pair. The other sides of load resistors 16 and 17, and the collectors of transistors 18 and 19, are connected to a terminal means, 20, adapted for connection to a source of relatively positive voltage.
Transistors 14 and 15 are cross-coupled transistors in that the collector of one is connected through an output transistor to the emitter of the other. Thus, the emitter of output transistor 18 is connected to the base of transistor 15, and the base of transistor 18 is connected to the collector transistor 14. Similarly, the emitter output transistor 19 is connected to the base of transistor 14, and the base of transistor -9 is connected to the collector of transistor 15.
Relatively positive voltage, applied to terminal 20, is taken with respect to a further terminal, 21, serving as the reference voltage or ground terminal and adapted for connection to a voltage supply also. A current sink arrangement is connected to terminal 21 formed by a further npn bipolar transistor, 22, and a resistor, 23, connected between the emitter of transistor 22 and terminal 21. The base of transistor 22 is adapted for connection to a reference voltage supplied to a further terminal, 24.
The emitters of the cross-coupled transistors 14 and 15 are also connected to this current sink means at the collector of transistor 22 through a further npn bipolar transistor, 25, having its base connected to a terminal, 27. The emitters of input transistors 10 and 11 are connected to this current sink at the collector of transistor 22 through a further npn bipolar transistor, 26. Supplying a signal to a terminal, 28, and so to the base of transistor 26 connected thereto, sufficient to switch it into "on" condition allows transistor 26 to pass the current drawn by the current sink means containing transistor 22 as supplied by input transistors 10 and 11. This arrangement allows signals at the bases of transistors 10 and 11 to set the logic states at the collectors thereof, and so at the outputs of the cross-coupled circuit involving transistors 14 and -5. Typically, the base of transistor 11 might be connected to a reference voltage and the base of transistor 10 may be connected to a source of logic signals which alternate between two voltage states on either side of the voltage value supplied to the based of transistor 11. Alternatively, complementary logic signals can be provided at the base of input transistors 10 and 11.
Similarly, the supplying of voltage to terminal 27, and so to the base of transistor 25 to switch it into the "on" condition, allows the voltage states established at the collectors of input transistors 10 and 11 to also be established and then maintained in the circuit involving cross-coupled transistors 14 and 15. These maintained states persist until subsequently altered by enablement of transistor 26 and input transistors 10 and 11. Thus, transistors 25 and 26 serve as latch circuit control transistors. The base of transistor 25 may typically be connected to a reference voltage applied to terminal 27 to which it is connected. The base of transistor 26 is shown connected to terminal 28 as a source of logic signals. The signal source for terminal 28 can operate between two voltage levels on either side of a reference voltage supplied to terminal 27. Transistor 26, in the "on" condition, allows establishment of selected voltage states at the collectors of input transistors 10 and 11 by the voltage states provided to the bases thereof, or alternatively by the voltage state and reference voltage applied to these inputs.
Output transistors 18 and 19 are provided to supply current in addition to what could be supplied through resistors 16 and 17, respectively, to operate the bases to which the emitters of these transistors are connected, and, in many instances, to provide the latch circuit outputs. In many situations, however, such additional current supply will not be needed and transistors 18 and 19 will be eliminated from the circuit. In such situation, the connections shown by the dashed lines in FIG. 1 will be provided instead. The resulting latch circuit outputs, 29 and 29', are shown for this latter situation.
As can be seen in FIG. 1, certainly for either transistors 14 or 15, there will always be one transistor in the "off" condition. In a situation where transistor 26 is in the "off" condition and transistor 25 in the "on" condition, the state of transistors 14 and 15 determine what information is being stored in the latch circuit. Thus, one of the transistors in the "on" condition and the other in the "off" condition defines one output logic state, and the opposite situation defines the other.
As indicated above, however, the transistor in the "off" condition, and having its collector-base junction reverse-biased, is subject in a radiation particle impingement situation to suddenly having that collector rapidly drop in voltage if radiation induced charge suddenly accumulates thereon. Such a sharp change in voltage, because of the cross-coupled feedback arrangement, will be propagated through to the base of the opposite transistor with a resulting risk of having the state of the latch circuit with these two cross-coupled transistors change from that logic state that had been present before the collector's sudden voltage drop to the opposite state. Thus, there is desired an improvement to the circuit of FIG. 1 to permit it to maintain logic states therein despite radiation particle impingement on reserve-biased junctions therein.